Apparatuses and methods for counter update operations

ABSTRACT

The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.16/905,030, filed on Jun. 18, 2020, which is a Continuation of U.S.application Ser. No. 15/958,614, filed on Apr. 20, 2018, and now issuedas U.S. Pat. No. 10,719,248 on Jul. 21, 2020, the contents of which areincorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory andmethods, and more particularly, to apparatuses and methods for counterupdate operations.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits and/or external removable devices in computers orother electronic devices. There are many different types of memoryincluding volatile and non-volatile memory. Volatile memory can requirepower to maintain its data and can include random-access memory (RAM),dynamic random access memory (DRAM), and synchronous dynamic randomaccess memory (SDRAM), among others. Non-volatile memory can providepersistent data by retaining stored data when not powered and caninclude NAND flash memory, NOR flash memory, read-only memory (ROM), andresistance variable memory such as phase change random access memory(PCRAM), resistive random access memory (RRAM), and magnetic randomaccess memory (MRAM), among others.

Memory devices can be utilized as volatile and non-volatile memory for awide range of electronic applications in need of high memory densities,high reliability, and low power consumption. Non-volatile memory may beused in, for example, personal computers, portable memory sticks, solidstate drives (SSDs), personal digital assistants (PDAs), digitalcameras, cellular telephones, portable music players, for example, MP3players, and movie players, among other electronic devices. Data, suchas program code, user data, and/or system data, such as a basicinput/output system (BIOS), are typically stored in non-volatile memorydevices.

One of a number of states (e.g., resistance states) can be set for aresistance variable memory cell. For example, a single level cell (SLC)may be programmed (e.g., written) to one of two states (e.g., logic 1 or0), which can depend on whether the cell is programmed to a resistanceabove or below a particular level. As an additional example, variousresistance variable memory cells can be programmed to one of multipledifferent states corresponding to respective digit patterns (e.g., 10,01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc.). Such cells maybe referred to as multi state cells, multi-digit cells, and/ormultilevel cells (MLCs).

The state of the memory cell can be determined (e.g., read), forexample, by sensing current through the cell responsive to an appliedinterrogation voltage. The sensed current, which varies based on avoltage level of the cell, can indicate the state of the cell (e.g., thebinary data stored by the cell). However, the voltage level of the cellmay undesirably change due to various reasons, which can result inerroneous sensing of a memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem including a memory system capable of performing counter updateoperations in accordance with a number of embodiments of the presentdisclosure.

FIG. 2 illustrates a diagram of an example physical block having anumber of physical pages in accordance with a number of embodiments ofthe present disclosure.

FIG. 3A illustrates a timing diagram associated with updating countersassociated with a write operation.

FIG. 3B illustrates a timing diagram associated with updating countersassociated with a read operation.

FIG. 3C illustrates a timing diagram associated with performing acounter update operation in accordance with a number of embodiments ofthe present disclosure.

FIG. 4 illustrates a diagram associated with performing an examplecounter operation during a read operation in accordance with a number ofembodiments of the present disclosure.

FIG. 5 illustrates a diagram associated with performing an examplecounter update operation during a write operation in accordance with anumber of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods for performingcounter update operations. An example apparatus comprises a memoryincluding a managed unit that includes a plurality of first groups ofmemory cells and a second group of memory cells, in which respectivecounters associated with the managed unit are stored on the second groupof memory cells. The example apparatus further includes a controller.The controller includes a core configured to route a memory operationrequest received from a host and a datapath coupled to the core and thememory. The datapath may be configured to issue, responsive to a receiptof the memory operation request routed from the core, a plurality ofcommands associated with the routed memory operation request to thememory to perform corresponding memory operations on the plurality offirst groups of memory cells. The respective counters may be updatedindependently of the plurality of commands.

A number of counters (e.g., read/write counters) may be utilized todetermine when to “refresh” cells (e.g., setting the cells back to theirtarget state). For example, a read signal and/or a write signal appliedto the cells may undesirably alter (e.g., read/write disturbs) a stateof a particular cell (e.g., to which the signals are applied) as well asthose neighboring cells (e.g., cells adjacent to the particular cell),which results in an erroneous determination of a logical state of thecells. Accordingly, the number of counters may be utilized to identify adegree of influence of the signals on, for example, neighboring cells,and may determine when to refresh those neighboring cells to correctlysense a logical state of the cells.

Embodiments of the present disclosure provide various benefits such asreduced latencies associated with a memory device capable of updatingcounters (e.g., read/write counters) compared to previous approaches.For example, various previous approaches associated with updatingcounters include retrieving the counters from an array of memory cells,updating the retrieved counters at a different device than a deviceincluding the array of memory cells, and/or storing the retrievedcounters back to the array of memory cells where the counters werepreviously stored. Such an approach can require constantly communicatinginformation (e.g., transferring data) among the associated devices,which may result in undesired latencies associated with communicatingthe information and/or may be costly in terms of energy consumption byrequiring a number of undesired sensing/programming of cells (e.g.,which would further results in reduced data reliability and/or dataintegrity). In contrast, a number of embodiments of the presentdisclosure can provide counter update operations in a manner thatreduces latencies associated with communicating information (e.g.,read/write counters) and reducing energy consumption as compared toprior approaches.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical, andstructural changes may be made without departing from the scope of thepresent disclosure.

As used herein, designators such as “N” and “M”, particularly withrespect to reference numerals in the drawings, indicate that a number ofthe particular feature so designated can be included. It is also to beunderstood that the terminology used herein is for the purpose ofdescribing particular embodiments only, and is not intended to belimiting. As used herein, the singular forms “a”, “an”, and “the” caninclude both singular and plural referents, unless the context clearlydictates otherwise. In addition, “a number of” something (e.g., a numberof memory cells) can refer to one or more of such things, whereas a“plurality of” is intended to refer to more than one of such things(e.g., more than one memory cell). Furthermore, the words “can” and“may” are used throughout this application in a permissive sense (e.g.,having the potential to, being able to), not in a mandatory sense (e.g.,required to).

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 110 may referenceelement “10” in FIG. 1, and a similar element may be referenced as 310in FIG. 3.

Ordinal numbers such as first and second are used herein to assist incorrelating and/or distinguishing between similar and/or selectablycoupled components (e.g., groups of memory cells, materials, etc.) andare not used to indicate a particular ordering and/or relationshipbetween the components, unless the context clearly dictates otherwise(e.g., by using terms such as adjacent, etc.).

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem 100 including a memory system 104 capable of performing counterupdate operations in accordance with a number of embodiments of thepresent disclosure. As used herein, a memory system 104, a systemcontroller 110, or a memory device 116 might also be separatelyconsidered an “apparatus.” The memory system 104 can be a solid statedrive (SSD), for example, and can include a host interface 106, a systemcontroller 110, and a memory device 116, which can serve as a memory forsystem 104.

The system controller 110 can be coupled to the host 102 via hostinterface 106 and to the memory device 116 via memory interface 108, andcan be used to transfer data between the memory system 104 and a host102. The host interface 106 can be in the form of a standardizedinterface. For example when the memory system 104 is used for datastorage in a computing system 100, the host interface 106 can be aserial advanced technology attachment (SATA), peripheral componentinterconnect express (PCIe), or a universal serial bus (USB), amongother connectors and interfaces. In general, the memory system 104 andthe host 102 that are coupled to each other via the host interface 106may each have a compatible receptor for passing control, address, data,and other signals via the host interface 106. Similarly, the systemcontroller 110 and the memory device 116 may each have a receptorcompatible with the memory interface 108. The memory interface 108 maysupport various standards and/or comply with various interface types(e.g., DDR, ONFI, etc.).

Host 102 can include a system motherboard and/or backplane and caninclude a number of memory access devices (e.g., a number ofprocessors). Host 102 can also be a memory controller, such as wherememory system 104 is a memory device (e.g., a memory device having anon-die controller). As an example, assuming that the computing system100 is a cellular phone (e.g., smartphone), the host 102 may be a systemon a chip (SoC) and the memory system 104 can be an embedded Multi-MediaController (eMMC) and/or Universal Flash Storage (UFS).

The system controller 110 can communicate with the memory device 116(which in some embodiments can be a number of memory arrays on a singledie and/or a number of dies) to control data read, write, and eraseoperations, among other operations. The system controller 110 can becoupled to the memory interface 108 coupling the system controller 110to the memory device 116. The system controller 110 can include, forexample, a number of components in the form of hardware and/or firmware(e.g., one or more integrated circuits) and/or software for controllingaccess to the memory device 116 and/or for facilitating data transferbetween the host 102 and memory device 116.

In some embodiments, the system controller 110 may be a non-volatilememory express (NVMe) controller. For example, the system controller 110may be configured to operate in accordance with a logical deviceinterface specification (e.g., protocol) such as the NVMe specificationor a non-volatile memory host controller interface specification.Accordingly, in some embodiments, the system controller 110 may beconfigured to process commands according to the NVMe protocol.

The system controller 110 can include a core component 112 and adatapath component 114. The core component 112 can be configured toperform various functions such as receiving a memory operation request(e.g., request to perform operations on the memory device 116) from thehost 102 and route the request to a datapath component 114. The datapathcomponent 114 can be configured to generate, responsive to a receipt ofthe routed request, commands associated with the routed request andissue the commands to the memory device 116.

In some embodiments, the datapath component 114 can serve as an arbitercomponent, which can be configured to perform various functions such ascoordinating commands performed on memory device 116. In someembodiments, the datapath component 114 can serve as a sequencercomponent, which can be configured to perform various functions such assequencing commands to be issued to the memory device 116 such thatoperations corresponding to the commands may be performed within thememory device 116 as sequenced by the datapath component 114.

The memory device 116 can include a number of memory arrays (not shown)and a control logic 118 (e.g., memory controller). The control logic 118can be located internal to the memory device 116 and can receivecommands (e.g., write commands, read commands, refresh commands, etc.)from the system controller 110 via the memory interface 108. Asdescribed further herein, the control logic 118 can be configured tomanage (e.g., update) counters stored in the memory device 116independently of the host 102 (e.g., without assistance from externalcontroller such as the host 102). Stated differently, the control logic118 can be configured to perform the counter update operation despitethat the system controller 110 does not cause the control logic 118 toperform the counter update operation. Accordingly, the control logic 118can be configured to update the counters without transferring thecounters back to the system controller 110.

In some embodiments, the system controller 110 may not cause the controllogic 118 to perform the counter update operation unless requested bythe control logic 118. For example, the control logic 118 may performthe counter update operations independently of the system controller 110(e.g., absent a direction issued from the system controller 110) by, forexample, incrementing/decrementing a respective counter value until athreshold is reached. When the threshold is reached, the control logic118 may request a direction from the system controller 110. In thisevent, responsive to the request from the control logic 118, the systemcontroller 110 may issue a direction associated with what to do when thethreshold is reached (e.g., increment, decrement, and/or reset). Assuch, in some embodiments, the system controller 110 may be offloadedfrom burdens of performing counter update operations by allocating aportion of the burdens to the control logic 118.

In a number of embodiments, updating counters (e.g., by the controllogic 118) may include incrementing values of the counters, for example,until a threshold value is reached, decrementing/resetting values of thecounters, for example, when a state of memory cells are refreshed,and/or alerting (e.g., interrupt signal) the host 102 and/or the systemcontroller 110 when any one of the counters reaches a threshold value.In some embodiments, a read counter may be incremented each timecorresponding memory cells are read. Similarly, a write counter may beincremented each time corresponding memory cells are programmed (e.g.,written). The terms “program” and “write” are used interchangeablyherein and may have the same meaning, as appropriate to the context.

In some embodiments, counters (e.g., at least a portion of the counters)may have a plurality of thresholds. For example, a particular counter(e.g., read and/or write) may include two different thresholds, and eachof the two different thresholds may be utilized to further define whatcourse of action, for example, the memory device 116 can take when eachthreshold is reached. As an example, the memory device 116 may beconfigured to send an alert to the host when one threshold (e.g., lower)is met for the particular counter and further configured to reset (e.g.,saturate) the particular counter when another threshold (e.g., higher)is met. The terms “reset” and “saturate” are used interchangeably hereinand may have the same meaning, as appropriate to the context.

In some embodiments, resetting values may include adjusting values to aninitial value (e.g., 0 and/or a predetermined value such as X). Forexample, when a particular value reaches a threshold, the particularvalue may be adjusted (e.g., reset) to the initial value such that theparticular value may again be incremented/decremented without exceedingthe threshold value. Values may be reset each the threshold value is met(e.g., reinitialization).

In some embodiments, different types of counters may be employed for thecomputing system 100. The different types of counters may include, forexample, a read counter that can be particularly utilizable for a cachememory such that it may be reset more frequently than it would have beenhad the read counter utilized for main memory (e.g., memory device 116).The different types of counters may include, for example, two differentwrite counters such that one of the two different write counters can beutilized for memory operations (e.g., read/write operations) and anotherone of the two different write counters can be utilized for wearleveling operations.

In a number of embodiments, the memory array(s) of memory device 116 cancomprise non-volatile memory cells. For example, the memory cells of thememory array may be resistance variable memory cells such as PCRAMand/or RRAM. As an example, the memory cells can be phase change memory(PCM) cells, which can be chalcogenide-based memory cells including asingle chalcogenide material serving as both a storage elements and aswitch elements for the cells and/or a stack of materials with a firstchalcogenide material serving as a switch element and a secondchalcogenide serving as a storage element for the cells. However,embodiments are not so limited. For example, memory arrays of the memorydevice 116 may comprise NAND flash memory cells and/or NOR flash memorycells, among others.

Memory cells (e.g., resistance variable memory cells) may be rewritable.For example, a particular data pattern can be programmed to a group ofresistance variable memory cells without necessarily erasing datapreviously stored in the group.

In operation, data can be written to and/or read from memory device 116as a block of data, for example. As such, a block of data can bereferred to as a data transfer size of the memory system 104. Data canbe sent to/from a host (e.g., host 102) in data segments referred to assectors (e.g., host sectors). As such, a sector of data can be referredto as a data transfer size of the host. In a number of embodiments, thememory device 116 can store managed units in respective blocks of memorycells (e.g., resistance variable memory cells). As used herein, amanaged unit may be referred to as a number of memory cells that areprogrammed and/or read together or as a functional group.

A managed unit may correspond to a logical block size (e.g., a datatransfer size of a host such as host 102) and/or a data management sizeof a memory system (e.g., memory system 104), which can be, for example,4 KB. As an example, a managed unit can be mapped (e.g., via systemcontroller 110) to a physical block of memory cells. However,embodiments are not so limited. For example, a managed unit maycorrespond to more than a logical block size when a group of memorycells storing user data and overhead data (e.g., data informative ofother data stored within the group of memory cells) corresponds to morethan a logical block size. As an example, the overhead data may includedata such as metadata, error correction code (ECC) data, logical blockaddresses (LBA) data as well as counters (e.g., read/write counters)associated with memory operations performed on a managed unit (e.g.,physical block 220).

In a number of embodiments, a managed unit may include different typesof groups of memory cells. For example, the managed unit may include aplurality of first groups of memory cells and a second group of memorycells, in which counters associated with the managed unit may be storedon the second group of memory cells. As described herein, a “group ofmemory cells” may correspond to a page of memory cells.

FIG. 2 illustrates a diagram of an example physical block 220 having anumber of physical pages 222-0 (PAGE 0), 222-1 (PAGE 1), . . . , 222-N(PAGE N) in accordance with a number of embodiments of the presentdisclosure. In a number of embodiments, the example physical block 220may be a managed unit as described in connection with FIG. 1. Forexample, a physical block of cells can refer to a number of memory cellsthat are programmed and/or read together or as a functional group.

The block 220 may include a number of pages 222-0 (PAGE 0), 222-1 (PAGE1) 222-N (PAGE N) (e.g., collectively referred to as pages 222). As anexample, the number of physical pages 222 may be 128 pages with eachpage corresponding to 32 bytes page size. As such, the block 220 alsocan correspond to 4 KB bytes block size. However, embodiments are not solimited. For example, the number of physical pages 222 may be 516 pages,1024 pages, etc. and a block size of the block 220 can vary based on apage size of each page (e.g., pages 220) and a number of pages the block220 includes.

In some embodiments, physical pages 222-0, . . . , 222-(N−1) may beutilized to store user data, and a physical page 222-N may be utilizedto store overhead data, such as metadata, error correction code (ECC)data, logical block addresses (LBA) data as well as counters (e.g.,read/write counters) associated with memory operations performed on amanaged unit (e.g., physical block 220). In some embodiments, more thanone physical page (e.g., physical page 222-N) may be allocated to storethe overhead data.

The physical page 222-N is illustrated in greater detail in FIG. 2. Asillustrated in FIG. 2, the physical page 222-N includes a first portion224 and a second portion 226 that may be utilized to store differenttypes of data. In some embodiments, data stored on the first portion 224may be metadata including integrity data such as error data (e.g., errordetecting and/or correcting code data). In some embodiments, data storedon the first portion 224 may be information related to a particularphysical block (e.g., logical block address corresponding to theparticular physical block) which may be used by the system controller110.

The second portion 226 of the physical page 222-N may include counterssuch as a read counter and/or a write counter. As used herein, a readcounter may be referred to as a value indicating a quantity of readoperations performed on a managed unit (e.g., physical block 220), forexample, relative to a quantity of read operations performed on managedunits. As used herein, a write counter may be referred to as a valueindicating a quantity of write operations performed on a managed unit(e.g., physical block 220), for example, relative to a quantity of writeoperations performed on managed units.

As an example, in which a physical page 222 corresponds to a page sizeof 32 bytes, the first portion 224 that stores the user data cancorrespond to 30 bytes, and the second portion 226 that stores thecounters (e.g., read/write counters) can correspond to 2 bytes (e.g., 1byte for each of the counters). However, embodiments are not so limited.For example, size of counters may vary such that, in some embodiments,read and write counters may be 8-bit each, and/or, in some embodiments,a size of a read counter may correspond to 16 bits while a size of awrite counter may correspond to 32 bits.

Having a relatively small size for a managed unit (e.g., physical block220 corresponding to a block size of 4 KB) may provide benefits such asenabling the control logic 118 to manage counters stored in the managedunit, as compared to those approaches having a block corresponding to ablock size of 512 KB, 1.024 MB, etc. For example, the control logic 118may be restricted in terms of a circuit design due to a size/design ofthe memory device 116 such that the circuit design of the control logic118, in some embodiments, may need to be simplified as compared to thesystem controller 110. As such, the control logic 118 with thesimplified circuit design may not be capable of managing counters forthose blocks corresponding to a relatively large block size such as 512KB, 1.024 MB, etc. In contrast, embodiments of the present disclosurereduce a size of each managed unit managed by the control unit 118,which provides benefits of enabling counter management independently ofthe system controller 110.

FIG. 3A illustrates a timing diagram 330 associated with updatingcounters associated with a write operation 336. The counters may beupdated (e.g., managed) by a system controller 310, which can be acontroller such as the system controller 110 that includes the corecomponent 112 (e.g., analogous to a core component 312) and the datapathcomponent 114 (e.g., analogous to a datapath component 314) as describedin connection with FIG. 1. In this example, the write operation 336 isan operation requested by a host (e.g., host 102) to be performed on amemory device 316. A read operation 332 is an operation performed toobtain (e.g., retrieve) counters to be updated via a counter updateoperation 334.

In this example, at a time t₁, the core 312 sends a counter request tothe datapath 314. For example, the counter request may be a request forretrieving (e.g., reading) counters (e.g., write counters) associatedwith a physical block address (PBA) to which the write operation 336 isto be performed. The datapath 314 generates a command (e.g., “read cmd”)corresponding to the received counter request, and sends, at time t₂,the generated command to the memory device 316. At time t₃, the countersretrieved from the memory device 316 are received at the datapath 314,which routes, at a time t₄, the retrieved counters to the core 312. Assuch, at some point subsequent to t₄, the counters may be updated by thecore 312 via a counter update operation 334. The updated counters may bestored back to the memory device 316 via the write operation 336. Forexample, at a time t₅, the core 312 sends a write request (e.g., toperform the write operation 336) to the datapath 314, which generateswrite commands (e.g., “write cmd”) corresponding to the write requestand sends, starting from a time t₆, the generated write commands to thememory device 316. As an example, when the write operation 336 is to beperformed on one of the managed units (e.g., block 220) of the memorydevice 316, each of the generated write commands may be directed to acorresponding page of the managed unit.

As illustrated in FIG. 3A, when the counters associated with the writeoperation 336 are managed (e.g., updated) by the system controller 310,the system controller 310 may need to obtain information associated withthe counters prior to writing back the updated counters to the memorydevice 316. Accordingly, the read operation 332 that is separate fromthe write operation 336 needs to be performed to obtain the counters.

FIG. 3B illustrates a timing diagram 340 associated with updatingcounters associated with a read operation 342. The counters may beupdated (e.g., managed) by a system controller 310, which can be acontroller such as the system controller 110 that includes the corecomponent 112 (e.g., analogous to a core component 312) and the datapathcomponent 114 (e.g., analogous to a datapath component 314) as describedin FIG. 1. In this example, the read operation 342 is an operationrequested by a host (e.g., host 102) to be performed on a memory device316. A write operation 346 is an operation performed to obtain (e.g.,retrieve) counters to be updated via a counter update operation 344.

In this example, at a time t₁, the core 312 sends a request (e.g., readrequest) to perform the read operation 342 on the memory device 316(e.g., a block of the memory device 316). The datapath 314 generates acommand (e.g., read commands as illustrated in FIG. 3B) corresponding tothe request, and sends, starting from a time t₂, the generated commandsto the memory device 316.

Data requested to be read (e.g., as specified by read commands) may beretrieved (e.g., returned) to the datapath 314 at a time t₃. Datapath314 routes, at a time t₄, the received data to the core 312 such thatthe core 312 further returns the retrieved data to the host (e.g., host102). The retrieved data (e.g., retrieved to the host) may includecounters (e.g., read counters associated with a physical block addressto which the write operation 346 is to be performed). As such, uponreceiving the counters (e.g., at the system controller 310), thecounters may be updated by the system controller 310 at some timebetween t₄ (e.g., subsequent to receiving the counters at the core 312)and t₅ (e.g., prior to sending a request to write the updated countersback to the memory device 316).

To write (e.g., store) the updated counters back to the memory device316, another operation (e.g., write operation 346) that is separate fromthe read operation 342 needs to be performed. For example, at a time t₅,the core 312 sends a counter request (e.g., to write the updatedcounters back to the memory device 316) to the datapath 314, whichgenerates a write command (e.g., “write cmd”) corresponding to thecounter request, and sends, at a time t₆, the generated write command toa particular location (e.g., where the counters were previouslyretrieved from) of the memory device 316.

When counters are managed (e.g., updated) by a controller, such as thesystem controller 110, updating counters associated with a writeoperation (e.g., as illustrated in FIG. 3A) and a read operation (e.g.,as illustrated in FIG. 3B) may require an operation that is separatefrom the associated write and read operations 336, 342. For example,counters associated with the write operation 336 of FIG. 3A may not beupdated without a separate read operation 332 because the systemcontroller 310 needs to identify a value corresponding to the countersprior to updating and writing back to the memory device 316. Similarly,counters associated with the read operation 342 of FIG. 3B may not beupdated without a separate write operation 346 because, although thecounters may be read by the read operation 342, the updated countersneed to be written back to the memory device 316, which may not beperformed by the read operation 342.

FIG. 3C illustrates a timing diagram 350 associated with performing acounter update operation in accordance with a number of embodiments ofthe present disclosure. A write operation 352 and a read operation 354illustrated in FIG. 3C may be operations requested by a host (e.g., host102) The counters may be updated (e.g., managed) by, for example, acontrol logic (e.g., control logic 118 of FIG. 1) of a memory device316.

In this example, at a time t₁, the core 312 sends a request to perform awrite operation 352 on the memory device 316 (e.g., a block of thememory device 316). For example, the request to perform the writeoperation may be a request received from a host (e.g., host 102). Thedatapath 314, responsive to receiving the request from the core 312,generates a command (e.g., “write cmd”) corresponding to the request,and sends, starting from a time t₂, the generated commands to the memorydevice 316. As an example, when the write operation 352 is to beperformed on one of managed units (e.g., block 220) of the memory device316, each of the generated write commands may be directed to acorresponding page of the managed unit.

In this example, at a time t₃, the core 312 sends a request to perform aread operation on the memory device 316 (e.g., a block of the memorydevice 316). For example, the request to perform the read operation 354may be a request received from a host (e.g., host 102). The datapath314, responsive to receiving the request from the core 312, generates acommand (e.g., “read cmd”) corresponding to the request, and sends,starting from a time t₄, the generated commands to the memory device316. As an example, when the read operation 354 is to be performed onone of managed units (e.g., block 220) of the memory device 316, each ofthe generated read commands may be directed to a corresponding page ofthe managed unit. Data requested to be read (e.g., as specified by readcommands) may be retrieved (e.g., returned) to the datapath 314 at atime t₅. Datapath 314 routes, at a time t₆, the received data to thecore 312 such that the core 312 further returns the retrieved data tothe host (e.g., host 102). In a number of embodiments, the dataretrieved at a time t₆ from the memory device 316 may be free of (e.g.,may not include) information associated with counters (e.g., countervalues).

In a number of embodiments, commands generated by the datapath 314 andissued to the memory device 316 may be free of instructions to cause thememory device 316 (e.g., control logic 118) to update the counters.Stated differently, commands issued starting from a time t₂ and t₄ mayinclude instructions to cause the control logic 118 to performcorresponding memory operations (e.g., read/write operations 352, 354)while the same commands may be free of (e.g., may not include)instructions to cause the control logic 118 to perform the counterupdate operations. Accordingly, the control logic 118 can be configuredto perform a counter update operation independently of the systemcontroller 110 and/or the host 102 while being configured to performmemory operations (e.g., requested by the host 102) dependently of thereceived commands.

Further, the counter update operation performed as illustrated in FIG.3C is embedded within the write operation 352 and/or the read operation354 in that it can be performed without a separate read operation (e.g.,such as the read operation 332 for the write operation 336) and/or aseparate write operation (e.g., such as the write operation 344 for theread operation 342). Also, unlike the counter update operation describedin FIGS. 3A and 3B, which is performed responsive to a request from thecore 312 that is separate from a request to perform a read operation 336and/or a write operation 342, the counter operation embedded withincorresponding memory operations may be performed responsive to anindividual request that would also trigger performing the correspondingmemory operations.

FIG. 4 illustrates a diagram 450 associated with performing a counterupdate operation during a read operation in accordance with a number ofembodiments of the present disclosure. In this example illustrated inFIG. 4, the read operation may be an operation requested by a host(e.g., host 102) to be performed on blocks 420 (e.g., block 220). Forexample, a request to perform the read operation may be received at asystem controller (e.g., system controller 110), which generatescorresponding commands (e.g., by the datapath component 114) and sendsthe corresponding commands to a control logic (e.g., control logic 118).

As illustrated in FIG. 4, two different blocks 420-1 and 420-2 (e.g.,collectively referred to as blocks 420) are shown in FIG. 4. Each of theblocks may be a managed unit and partitioned into a number of addressspaces such that each of the number of address spaces may be controlledindependently of others. For example, each partitioned address space ofthe blocks may include a portion of a number of pages (e.g., of each ofthe blocks) such that a number of operations may be simultaneouslyperformed among pages of the same block. For example, the control logic118 may initiate a read operation (e.g., along with a counter updateoperation) corresponding to a command 452-N while a read operationcorresponding to a command 452-(N−1) is being performed. As an example,pages 454-(N−2), 454-(N−1), 454-N (e.g., of the block 420-1) may beassigned to a partition 1, 2, and 3, respectively, and pages 458-0,458-1, 458-2, and 458-3 may be assigned to a partition 0, 1, 2, and 3,respectively.

The block 420-1 may include a number of pages (e.g., N+1 pages)including a page 452-(N−1) and a page 452-N. For example, the page452-(N−1) (e.g., one of a plurality of first groups of memory cells) maycomprise user data, which can be read (e.g., retrieved to a host 102)via a read command 452-(N−1). For example, the page 452-N (e.g., asecond group of memory cells) may comprise overhead data along withcounters associated with the block 420-1. Accordingly, a counter updateoperation may be performed on the page 452-N.

In this example illustrated in FIG. 4, read commands 452 includingcommands 452-(N−1) and 452-N may be sequentially received prior to atime t₁. Accordingly, read operations on the pages 454 including pages454-(N−2), 454-(N−1), and 454-N may be sequentially initiated inresponse to the receipt of the read commands 452.

The command 452-(N−1) directed to a page 454-(N−1) is received (e.g., atthe control logic 118) at some time prior to a time t₁ as well as priorto a command 452-N. As such, in response to a determination that thepage 454-(N−1) comprises the user data, the control logic 118 canperform a read operation on the page 454-(N−1) by retrieving the userdata back to the system controller 110, which can further return theretrieved user data back to the host 102.

The command 452-N directed to a page 454-N is received (e.g., at thecontrol logic 118) at a time t₁. As such, in response to a determinationthat the page 454-N comprises the counters, the control logic 118 canupdate (e.g., perform a counter update operation) the counters (e.g.,read counters) in addition to performing the read operation as requestedby the host 102 and instructed by the command 452-N. For example, datastored on the page 454-N can be read from a t₁ to t₂ (e.g., “tRead”) andthe counters may be updated from t₂ to t₃ (e.g., “tCounterUpdate”). Theretrieved data (e.g., denoted as “454-N”) may be sent back to the systemcontroller 110 via a data bus such as a DQ bus.

In a number of embodiments, the counters may be updated without beingtransferred back to the system controller 110. Accordingly, in thisexample, the counters stored on the page 454-N may be simultaneouslyupdated while the overhead data (e.g., metadata) and the countersretrieved from the page 454-N may be sent back to the system controller110. For example, the metadata retrieved from the page 454-N may besent, at a time t₂, back to the system controller 110, and the countersmay be updated also at a time t₂. Therefore, latencies associated withtransferring the counters between the memory device 116 and the systemcontroller 110 may be eliminated in updating the counters.

In some embodiments, the counters may be buffered to be updated at alater time (e.g., subsequent to a time t₂). Instead of being updated att₂, the counters may be, for example, buffered (e., from being updated)until an internal resource is readily available for updating thecounters such that other operations (e.g., read/write operations) arenot adversely affected by latencies associated with updating thecounters.

In this example illustrated in FIG. 4, write commands 456 includingcommands 456-0, 456-1, 456-2, and 456-3 may be sequentially receivedsubsequent to a time t₁, and write operations on the pages 458 includingpages 458-0, 458-1, 458-2, and 458-3 may be sequentially initiated inresponse to the receipt of the write commands 566. While the countersare being updated, another operation (e.g., read operation) may beinitiated on another block 420-2. For example, those pages 458-0, 458-2,and 458-3 that are assigned to a different partition (e.g., addressspace) than the page 454-N may be read simultaneously with the counterupdate operation being performed on the page 454-N.

In some embodiments, the data stored on the page 454-N may not beretrieved to the system controller 110. In this example, rather thanproviding the data stored on the page 454-N to the system controller110, the control logic 118 may provide, at a time t₂, data stored on andretrieved from the page 458-1 via a data bus. As such, latenciesassociated with transferring the data stored on the page 454-N (e.g.,including the counters) may be eliminated in performing a number ofmemory operations on the memory device 116 (e.g., including the block420-1 and 420-2).

FIG. 5 illustrates a diagram 560 associated with performing a counterupdate operation during a write operation in accordance with a number ofembodiments of the present disclosure. In this example illustrated inFIG. 5, the write operation may be an operation requested by a host(e.g., host 102) to be performed on blocks 520 (e.g., block 220). Forexample, a request to perform the write operation may be received at asystem controller (e.g., system controller 110), which generatescorresponding commands (e.g., by the datapath component 114) and sendsthe corresponding commands to a control logic (e.g., control logic 118).

As illustrated in FIG. 5, two different blocks 520-1 and 520-2 (e.g.,collectively referred to as blocks 520) are shown in FIG. 5. Each of theblocks may be a managed unit and partitioned into a number of addressspaces such that each of the number of address spaces may be controlledindependently of others. For example, each partitioned address space ofthe blocks may include a portion of a number of pages (e.g., of each ofthe blocks) such that a number of operations may be simultaneouslyperformed among pages of the same block. For example, the control logic118 may initiate a write operation (e.g., along with a counter updateoperation) corresponding to a command 562-N while a write operationcorresponding to a command 562-(N−1) is being performed. As an example,pages 564-(N−3), 564-(N−2), 564-(N−1), and 564-N (e.g., of the block420-1) may be assigned to a partition 0, 1, 2, and 3, respectively, andpages 568-0, 568-1, 568-2, and 568-3 may be assigned to a partition 0,1, 2, and 3, respectively.

The block 520-1 may include a number of pages (e.g., N+1 pages)including a page 562-(N−1) and a page 562-N. For example, the page562-(N−1) (e.g., one of a plurality of first groups of memory cells) maycomprise user data, which can be written (e.g., retrieved to a host 102)via a write command 562-(N−1). For example, the page 562-N (e.g., asecond group of memory cells) may comprise overhead data and countersassociated with the block 520-1, which can be written via a writecommand 562-N. Accordingly, a counter update operation may be performedon the page 562-N.

In this example illustrated in FIG. 5, write commands 562 includingcommands 562-(N−1) and 562-N may be sequentially received from a timet₃. Accordingly, write operations on the pages 564 including pages564-(N−1) and 564-N may be sequentially initiated prior to a time t₃ inresponse to the receipt of the write commands 562.

The command 562-(N−1) directed to a page 564-(N−1) is received (e.g., atthe control logic 118) at some time prior to a time t₁ as well as priorto a command 562-N. For example, the command 562-(N−1) may include aninstruction to write a data pattern (e.g., user data received from thehost 102) as well as the data pattern to be stored on the page562-(N−1). As such, the control logic 118 can perform a write operationon the page 564-(N−1) by storing a data pattern received from the systemcontroller 110 (e.g., as from the host 102) on the page 564-(N−1).

The command 562-N directed to a page 564-N is received (e.g., at thecontrol logic 118) at a time t₁. For example, the command 562-N mayinclude an instruction to write a data pattern (e.g., overhead datareceived form the host 102) as well as the data pattern to be stored onthe page 562-N. In response to a receipt of the data pattern a time t₂,the control logic 118 can, from a time t₂ to a time t₄, update thecounters stored on the page 562-N in addition to (e.g., as well as)writing the received data pattern to the page 562-N.

As such, the control logic 118 can update the counters and write thedata by an individual write operation (e.g., by the write operationperformed from a time t₂ to a time t₄). Accordingly, a separateoperation such as a counter update operation may not be required forupdating the counters during a write operation. Stated differently, acounter update operation can be embedded within a write operationperformed on the page 564-N.

In this example illustrated in FIG. 5, write commands 566 includingcommands 566-0, . . . , 566-5 may be sequentially received from a timet₃, and write operations on the pages 568 including pages 568-0, . . . ,568-3 may be sequentially initiated from a time t₃ in response to thereceipt of the write commands 566. While the write operation is beingperformed on the page 564-N, another operation (e.g., write operations)may be initiated on another block 520-2. For example, data patterns(e.g., requested to be written to the block 520-2) may be written tothose pages 568-0 and 568-1 that are assigned to a different partition(e.g., partition 0 and partition 1) than the page 564-N (e.g., partition3) while the write operation is being performed on the page 564-N. Datapatterns may be initiated to be written to pages 568-2 (e.g., at a timet₄) and 568-3 (e.g., at a time t₅) in response to a receipt of writecommands 566-2 and 566-3, respectively.

In some embodiments, write operations can include operations that can bereferred to as read-modify-write (RMW) operations. For example, writinga data pattern to pages can include reading an entire page of data froman array of memory cells, updating the page with new data pattern, andthen writing the updated page back to the array of memory cells. Assuch, a read operation that can be performed as a part of the RMWoperation is an inherent operation of the RMW operation such that theread operation and a write operation of the same read-modify-writeoperation are performed by an individual operation. Accordingly, thosewrite operations illustrated in FIG. 5 may not need a read operationseparate from the write operations if the write operations are RMWoperations. In some embodiments, updating the counters can includeapplying a write signal only to those cells of pages whose states are tobe changed during a write operation.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of a number of embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of ordinary skill in the artupon reviewing the above description. The scope of a number ofembodiments of the present disclosure includes other applications inwhich the above structures and methods are used. Therefore, the scope ofa number of embodiments of the present disclosure should be determinedwith reference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

What is claimed is:
 1. A system, comprising: an array of memory cellscomprising a plurality of first groups of memory cells and a pluralityof second groups of memory cells; and a memory controller coupled to thearray and configured to: perform, responsive to receipt of a pluralityof commands, corresponding memory operations sequentially on theplurality of first groups of memory cells and the plurality of secondgroups of memory cells; and perform, independently of the plurality ofcommands, a counter update operation on the plurality of first groups ofmemory cells such that respective counters stored on one of theplurality of first groups are updated while a respective one of thecorresponding memory operations is being performed on one of theplurality of second groups of memory cells.
 2. The system of claim 1,wherein the plurality of commands are free of instructions to cause thememory controller to update the respective counters.
 3. The system ofclaim 1, wherein the memory controller is configured to perform a readoperation or a write operation to perform the counter update operation,wherein the counter operation is embedded within the read operation orthe write operation performed by the memory controller.
 4. The system ofclaim 1, wherein each one of the plurality of first groups and theplurality of second groups is assigned to a respective one of aplurality of partitions, and wherein the memory controller is configuredto simultaneously perform memory operations corresponding to groups ofthe plurality of first groups or the plurality of second groups that areassigned to different partitions.
 5. The system of claim 1, wherein theplurality of first groups or the plurality of second groups correspondsto a block of NAND memory cells and each group of the plurality of firstgroups or the plurality of second groups corresponds to a page of NANDmemory cells.
 6. The system of claim 1, wherein the one of the pluralityof first groups of memory cells further store overhead data.
 7. Thesystem of claim 6, wherein a remaining one of the plurality of firstgroups of memory cells store user data.
 8. A system, comprising: amemory device comprising a plurality of groups of memory cells, whereina first group of the plurality of groups of memory cells stores acounter associated with the plurality of groups of memory cells; and asystem controller coupled to the memory device, wherein the systemcontroller is configured to issue a command to read data from a secondgroup of the plurality of groups of memory cells; wherein the memorydevice is configured to, in response to receipt of the command from thesystem controller, update the counter stored in the first groupsimultaneously while the data read from the second group are beingtransferred to the system controller.
 9. The system of claim 8, whereinthe memory device is configured to perform read-modify-write (RMW)operation to update the counter without individually performing a readand a write operations to update the counter.
 10. The system of claim 8,wherein the memory device is configured to update the counter withoutreceiving a request to update the counter from the system controller.11. The system of claim 8, wherein the memory device is configured toupdate the counter without transferring the counter back to the systemcontroller.
 12. The system of claim 8, wherein the memory controller isconfigured to increment or decrement values of the respective countersuntil a threshold value is reached.
 13. The system of claim 8, whereinthe memory controller is configured to reset values of the respectivecounters to an initial value in response to a determination that valuesof the respective counters have reached a threshold value.
 14. Thesystem of claim 8, wherein the first group of the plurality furthercomprises metadata.
 15. The system of claim 8, wherein the systemcontroller is coupled to the memory device via a memory interfacecompliant with Double Data Rate (DDR), Open Nand Flash Interface (ONFI),or any combination thereof.
 16. A method, comprising: receiving aplurality of commands directed to a managed unit comprising: a firstgroup of memory cells storing respective counters associated with themanaged unit; and a second group of memory cells; and performing,independently of the plurality of commands, a counter update operationon the first group while a memory operation corresponding to the managedunit is being performed on the second group.
 17. The method of claim 16,wherein performing the counter update operation further comprisesperforming a corresponding memory operation, in which the counter updateoperation is embedded, and wherein the method further comprises:initiating performance of the corresponding memory operation on thefirst group, while performing the memory operation on the second group.18. The method of claim 16, wherein performing, independently of theplurality of commands, the counter operation comprises incrementing ordecrementing values of the respective counters until a threshold valueis reached.
 19. The method of claim 16, wherein: the memory operationperformed on the second group comprises a read-modify-write (RMW)operation; and the method further comprises applying a write signal onlyto those cells of the second group whose states are to be changed duringthe RMW operation.
 20. The method of claim 19, wherein performing thecounter update operation on the first group further comprises applying awrite signal only to those cells of the first group whose states are tobe changed during the RMW operation.